hardcaml-yosysversion
Import Verilog designs into HardCaml
| Author | Andy Ray |
|---|---|
| License | ISC |
| Published | |
| Homepage | https://github.com/ujamjar/hardcaml-yosys |
| Issue Tracker | https://github.com/ujamjar/hardcaml-yosys/issues |
| Maintainer | Andy Ray <andy.ray@ujamjar.com> |
| Dependencies | |
| Source [http] | https://github.com/ujamjar/hardcaml-yosys/archive/v0.1.0.tar.gz sha256=7abd70971b6216452e5bdff9ec5b825fc05a9a14c81e40422c0dd385725df973 md5=609fd6fa6a27104a97b59f9019f03a84 |
| Edit | https://github.com/ocaml/opam-repository/tree/master/packages/hardcaml-yosys/hardcaml-yosys.0.1.0/opam |
No package is dependent
