hardcamlversion
Register Transfer Level hardware design in OCaml
| Author | andy.ray@ujamjar.com |
|---|---|
| Published | |
| Homepage | https://github.com/ujamjar/hardcaml |
| Issue Tracker | https://github.com/ujamjar/hardcaml/issues |
| Maintainer | andy.ray@ujamjar.com |
| Dependencies |
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| Optional dependencies | |
| Source [http] | https://github.com/ujamjar/hardcaml/archive/v1.2.0.tar.gz sha256=f32f1626df956ea85c0bba349c34ba1b9cbe9e8ce95dd6ba0caed34d5ef3d05b md5=5bcb9e6198ba1c6e834adc752121e880 |
| Edit | https://github.com/ocaml/opam-repository/tree/master/packages/hardcaml/hardcaml.1.2.0/opam |
